During the past fifty years, the electronics and computing industries have been relentlessly propelled forward by the ever decreasing sizes of basic electronic components, such as transistors and signal lines, and by the correspondingly ever increasing component densities of integrated circuits, including processors and electronic memory chips. Eventually, however, it is expected that fundamental component-size limits will be reached in semiconductor-circuit-fabrication technologies based on photolithographic methods. As the size of components decreases below the resolution limit of ultraviolet light, for example, far more technically demanding and expensive higher-energy-radiation-based technologies need to be employed to create smaller components using photolithographic techniques. Not only must expensive semiconductor fabrication facilities be rebuilt in order to use the new techniques, many new obstacles are expected to be encountered. For example, it is necessary to construct semiconductor devices through a series of photolithographic steps, with precise alignment of the masks used in each step with respect to the components already fabricated on the surface of a nascent semiconductor. As the component sizes decrease, precise alignment becomes more and more difficult and expensive. As another example, the probabilities that certain types of randomly distributed defects in semiconductor surfaces result in defective semiconductor devices may increase as the sizes of components manufactured on the semiconductor services decrease, resulting in an increasing proportion of defective devices during manufacture, and a correspondingly lower yield of useful product. Ultimately, various quantum effects that arise only at molecular-scale distances may altogether overwhelm current approaches to component construction in semiconductors.
In view of these problems, researchers and developers have expended considerable research effort in fabricating microscale and nanoscale electronic devices using alternative technologies, where nanoscale electronic devices generally employ nanoscale signal lines having widths, and nanoscale components having dimensions, of less than 100 nanometers. More densely fabricated nanoscale electronic devices may employ nanoscale signal lines having widths, and nanoscale components having dimensions, of less than 50 nanometers.
Although general nanowire technologies have been developed, it is not necessarily straightforward to employ nanowire technologies to miniaturize existing types of circuits and structures. While it may be possible to tediously construct miniaturized, nanowire circuits similar to the much larger, current circuits, it is impractical, and often impossible, to manufacture such miniaturized circuits. Even were such straightforwardly miniaturized circuits able to feasibly manufactured, the much higher component densities that ensue from combining together nanoscale components necessitate much different strategies related to removing waste heat produced by the circuits In addition, the electronic properties of substances may change dramatically at nanoscale dimensions, so that different types of approaches and substances may need to be employed for fabricating even relatively simple, well-known circuits and subsystems at nanoscale dimensions. Thus, new implementation strategies and techniques need to be employed to develop and manufacture useful circuits and structures at nanoscale dimensions using nanowires.
Neural networks have been developed over the past 25 years as a useful tool for solving complex pattern matching and decision-making problems. Neural networks are often implemented in software, but may also be implemented as logic circuits. FIG. 1 illustrates a relatively simple, two-level neural network. In the example neural network shown in FIG. 1, there are three inputs 102-104. The neural network circuit is enclosed by a square dashed line 105. Based on the values of the three inputs 102-104, the neural network circuit 105 produces two outputs 106 and 107. The neural network shown in FIG. 1 includes two layers of nodes. The first layer comprises nodes 110-113 and the second layer of nodes comprises nodes 115 and 116. Each node receives, as input, a number of input signals, and produces an output signal. For example, node 110 receives, as input, signals 118 and 120, which are, in this case, input signals “in1” 102 and “in2” 103. Neural network node11 110 applies weighting factors w111 to input 118 and w211 to input 120, sums the two weighted inputs, and then outputs a signal that represents a function of the summed, weighted inputs. In the neural network shown in FIG. 1, node11 outputs signals 122 and 123 to second-level nodes node21 115 and node22 116, the output signal equal to ƒ11 (in1, in2), where ƒ11 is the function [w111 in1+w211 in2] carried out by node11 on the inputs “in1” 102 and “in2” 103. Each level-one node 110-113 receives some combination of input signals from inputs “in1” 102, “in2” 103, and “in3” 104. The signals output from the level-one nodes are input to the level-two nodes 115-116. In the neural network shown in FIG. 1, outputs of the level-two nodes are directly connected to the output signal lines 106 and 107, which represent the output of the neural-network circuit. The output of a neural network is thus a rather complex function of the input signals. For example, the output of the neural network shown in FIG. 1 to output signal line 106 may be described as follows:out1=ƒ21[ƒ11(in1, in2), ƒ12(in2+in3), ƒ13(in1, in2, in3)]=w121(w111in1+w211in2)+w221(w212in2+w312in3)+w321(w113in1+w213in2+w313in3)where                in1, in2, and in3 are the three signals input to the neural network;        wXyz is the weight applied to the xth input signal by nodeyz; and        ƒyz is the function implemented by nodeyz that transfers the weighted sum of the input signals of nodeyz to the output signal for nodeyz.        
Very complex multi-layered neural networks containing hundreds or thousands of nodes are currently employed, both in software implementations as well as in hardware circuits, to solve a number of complex computing problems. As with all hardware implementations, there is an increasing need for smaller and smaller scale implementations. Designers, manufacturers, and users of neural network circuits have recognized the need for implementing neural networks using nanoscale electronic circuitry. Unfortunately, the current methods by which neural networks are fabricated are not amenable to simple miniaturization using nanowire-based structures similar to those currently employed at larger dimensions. Instead, designers, manufacturers, and users of devices that include neural networks have recognized the need for new methods for implementing neural networks that are useable at nanoscale dimensions. Moreover, to facilitate reuse and flexibility of neural network components, designers, manufacturers, and users of devices that include neural networks have recognized the need for reprogrammable neural networks that can be reconfigured for alternative uses or to enhance the devices in which they are included.